1. Technical Field
The technical field relates to a liquid crystal display device, and more particularly to an apparatus and method for driving a liquid crystal display device that is adaptive for greatly reducing the sampling frequency of data which is supplied to a liquid crystal display panel.
2. Description of the Related Art
A liquid crystal display device controls the light transmittance of liquid crystal cells in accordance with a video signal to display a picture, and an active matrix type liquid crystal display device where a switching device is formed at each liquid crystal cell is advantageous in realizing a motion picture because it is possible to actively control the switching device. As shown in FIG. 1, the switching device used in the active matrix type liquid crystal display device is mainly a thin film transistor (hereinafter, referred to as “TFT”)
Referring to FIG. 1, the active matrix type liquid crystal display device converts digital input data into an analog data voltage on the basis of a gamma reference voltage to supply a data line DL, and simultaneously supplies a scan pulse to a gate line GL to charge a liquid crystal cell Clc.
A gate electrode of the TFT is connected to the gate line GL, a source electrode is connected to the data line DL, and a drain electrode of the TFT is connected to a pixel electrode of the liquid crystal cell Clc and one electrode of a storage capacitor Cst.
A common voltage Vcom is supplied to a common electrode of the liquid crystal cell Clc.
The storage capacitor Cst is charged with a data voltage supplied from the data line DL when the TFT is turned on, and acts to fixedly keep the voltage of the liquid crystal cell Clc.
If a scan pulse is applied to the gate line GL, the TFT is turned on to form a channel between the source electrode and the drain electrode, thereby supplying a voltage on the data line DL to the pixel electrode of the liquid crystal cell Clc. At this moment, liquid crystal molecules of the liquid crystal cell Clc have their arrangement changed by an electric field between the pixel electrode and the common electrode to modulate an incident light.
The configuration of the liquid crystal display device of the related art having the pixels with such a structure is described as shown in FIG. 2.
FIG. 2 is a configuration diagram of a driving apparatus of a liquid crystal display device of the related art.
Referring to FIG. 2, a driving apparatus 100 of the liquid crystal display device of the related art includes a liquid crystal display panel 110 where data lines DL1 through DLm cross gate lines GL1 through GLn and a thin film transistor TFT for driving a liquid crystal cell Clc is formed at each of the crossing parts and a data driver 120 for supplying data to the data lines DL1 through DLm of the liquid crystal display panel 110. Driving apparatus 100 also includes a gate driver 130 for supplying a scan pulse to the gate lines GL1 through GLn of the liquid crystal display panel 110 and gamma reference voltage generator 140 for generating a gamma reference voltage to supply to the data driver 120. The driving apparatus 100 further includes a backlight assembly 150 for irradiating light of the liquid crystal display panel 110 and an inverter 160 for applying an AC voltage and current to the backlight assembly 150. The driving apparatus 100 additionally includes a common voltage generator 170 for generating a common voltage Vcom, shown in FIG. 1, which is supplied to a common electrode of the liquid crystal cell Clc of the liquid crystal display panel 110. The driving apparatus 100 also includes agate drive voltage generator 180 for generating a gate high voltage VGH and a gate low voltage VGL, which are supplied to the gate driver 130, and a timing controller 190 for controlling the data driver 120 and the gate driver 130.
The liquid crystal display panel 110 has liquid crystal injected between two glass substrates. The data lines DL1 through DLm cross the gate lines GL1 through GLn on a lower glass substrate of the liquid crystal display panel 110. A TFT is formed at each of the crossing parts of the data lines DL1 to DLm and the gate lines GL1 to GLn. The TFT supplies data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to a scan pulse. A gate electrode of the TFT is connected to the gate line GL1 to GLn, and a source electrode of the TFT is connected to the data line DL1 to DLm. A drain electrode of the TFT is also connected to a storage capacitor Cst and a pixel electrode of the liquid crystal cell Clc.
The TFT is turned on in response to the scan pulse supplied to a gate terminal using the gate lines GL1 through GLn. Video data on the data lines DL1 through DLm is supplied to the pixel electrode of the liquid crystal cell Clc when turning on the TFT.
The data driver 120 supplies the data to the data lines DL1 through DLm in response to a data drive control signal DDC supplied from the timing controller 190, samples a digital video data RGB supplied from the timing controller 190 for latching, and then converts the gamma reference voltage supplied from the gamma reference voltage generator 140 into an analog data voltage. The analog data voltage can express the gray level in the liquid crystal cell Clc of the liquid crystal display panel 110 to supply the data lines DL1 to DLm.
The gate driver 130 sequentially generates the scan pulse, i.e., a gate pulse, to supply the gate lines GL1 through GLn in response to a gate drive control signal GDC and a gate shift clock GSC supplied from the timing controller 190. The gate driver 130 then determines the high level voltage and the lower level voltage of each scan pulse in accordance with the gate high voltage VGH and the gate low voltage VGL supplied from the gate drive voltage generator 180.
The gamma reference voltage generator 140 receives the highest potential supply voltage VDD in the supply voltages provided by the liquid crystal display panel to generate a positive gamma reference voltage and a negative gamma reference voltage, which are outputted to the data driver 120.
The backlight assembly 150 is disposed at the rear surface of the liquid crystal display panel 110, and is made to emit light from the AC voltage and current supplied from an inverter 160. The backlight assembly 150 is configured to irradiate the light to each pixel of the liquid crystal display panel 110.
The inverter 160 generates a square wave signal and then converts the square wave signal into a triangular wave signal. The inverter 160 then compares the triangular wave signal with a DC supply voltage supplied from the system to generate a burst dimming signal, which is proportional to the comparison result. If the inverter 160 generates the burst dimming signal determined in accordance with the internal square wave signal, a drive integrated circuit (not shown), which controls the generation of the AC voltage and current within the inverter 160, controls the generation of the AC voltage and current supplied to the backlight assembly 150 in accordance with the burst dimming signal.
The common voltage generator 170 receives the high potential supply voltage VDD to generate the common voltage Vcom, which is supplied to the common electrode of the liquid crystal cell Clc provided in each pixel of the liquid crystal display panel 110.
The gate drive voltage generator 180 receives the high potential supply voltage VDD to generate the gate high voltage VGH and the gate low voltage VGL, which are supplied to the gate driver 130. The gate drive voltage generator 180 generates the gate high voltage VGH, which is higher than a threshold voltage of the TFT provided at each pixel of the liquid crystal display panel 110, and generates the gate low voltage VGL, which is lower than the threshold voltage of the TFT. The generated gate high voltage VGH and the generated gate low voltage VGL are each used for determining a high level voltage and a low level voltage of the scan pulse generated by the gate driver 130.
The timing controller 190 supplies the digital video data RGB supplied from a digital video card (not shown) to the data driver 120, and generates the data drive control signal DDC and the gate drive control signal GDC by use of horizontal/vertical synchronization signals H, V in accordance with a clock signal CLK, thereby supplying the gate driver 120 and the gate driver 130 respectively. The data drive control signal DDC may include source shift clock SSC, source start pulse SSP, polarity control signal POL, source output enable signal SOE, or other similar signals. The gate drive control signal GDC may include gate start pulse GSP, gate output enable GOE, or other similar signals.
In one example, a semiconductor layer formed on the TFT of a pixel matrix array is formed using an amorphous Si. In another example, the semiconductor layer formed on the TFT of a pixel matrix array is formed using a Poly Si.
FIG. 3 is a schematic diagram of a data driver for supplying an analog data voltage to data lines in a liquid crystal display device using Poly Si as the semiconductor layer of the pixel matrix array.
Referring to FIG. 3, the data driver 120 for driving a data line of the liquid crystal display device using Poly Si as a semiconductor layer includes a decoder 121 for decoding inputted digital video data; a D/A converter 122 for converting the decoded digital video data into an analog data; and a sampling part 123 for sampling the analog data which is outputted by the D/A converter 122.
The decoder 121 decodes the inputted digital video data outputted by the timing controller 190 of FIG. 2 as output to the D/A converter 122.
The D/A converter 122 converts the digital video data decoded by the decoder 121 into the analog data as output to the sampling part 123.
The sampling part 123 sequentially samples the analog data outputted by the D/A converter 122 according to an output of a shift register 124, and supplies the sampled data to the data lines DL1 through DLm. The analog data is sequentially supplied to the (m)th data line DLm from a first data line D1 within a first horizontal time period. Accordingly, the output SR1 through SRm of the shirt register 124 is sequentially generated within the first horizontal time period. In other words, an analog data voltage is supplied to the first data line DL1 when the first pulse SR1 is generated, and the analog data voltage is supplied to the second data line DL2 when the second pulse SR2 is generated among the output of the shift register 124. The analog data voltage is sequentially supplied to the (m)th data line DLm from the first data line DL1 during the first horizontal time period according to a sequential supplying method.
As described above and shown in FIG. 4, the data sampling time is relatively long within the first horizontal time period, such that one analog data voltage charged into the data line is approximately an m/l horizontal time period 1H.
Referring to FIG. 5, the liquid crystal display device of the related art, the data supply time t1 for supplying the data to each data lines DL1 through DLm is greatly reduced. Thus, a data supply A2 cannot keep up with the output A1 of the D/A converter 122. As a result, the charge time in each pixel formed in the liquid crystal display panel 110 becomes short and the brightness of a display image is low. Hence, distortion is generated in the screen.